ASICs added to MEMS wafers

R. Colin Johnson
EE Times (11/01/2007 12:14 PM EDT)

PORTLAND, Ore. — Microelectromechanical system (MEMS) chips are currently joined to separate CMOS ASICs after separate wafers are diced. A new technique called "chip-on-MEMS" bonds ASIC dice atop an entire MEMS wafer before dicing, according to developer VTI Technologies Oy.

"Chip-on-MEMS is a radical step away from conventional packaging," said Heikki Kuisma, vice president of research at VTI, (Vantaa, Finland), a manufacturer of MEMS accelerometers and pressure sensors for the automotive market. "Now, even the final testing and calibration are wafer-scale processes."

Besides the benefit of wafer-scale calibration and testing, VTI Technologies also claims that Chip-on-MEMS will enable them to make much thinner chips. VTI has demonstrated a combined MEMS-ASIC measuring 4 mm2 but just 1-mm thick. Typical MEMS chips bonded to ASICs are between 2- and 5-mm thick. Eventually, VTI claims it will be able to produce chips-on-MEMS dice one-third the thickness of today's thinnest dice.

The chip-on-MEMS process works by first testing the MEMS wafer, then placing extra-thin ASIC dice face down on the MEMS wafer in known-good locations. Then 300-micron solder balls are dropped on the ASIC, which was flip-chipped with solder bumps.
Finally, an underfill isolates the ASIC from the MEMS for passivation and increased reliability. Final testing can then be performed at the wafer scale before dicing the combined chip-on-MEMS device.

Next, VTI said it is looking to stack multiple ASICs atop its MEMS wafers for producing 3D stacks of very complex circuitry. VTI said it hopes its technique will enable stacks of multiple 20-micron-thick ASICs to be integrated atop MEMS wafers at a much lower cost than competing 3D techniques. The company is also seeking to advance to technique to allow high-volume manufacturing.